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Checklist to help PCB and system designers complete a PCB.

Layers

At Least One Ground Plane Present

Every board must have at least one continuous ground plane to:

Provide a low-impedance power system.

Make the connection of low-impedance vias to device GND pins very
convenient.

Provides a path for return currents.

All of these are very important in for keeping ground noise at a minimum,
both on the board and in the devices.

Dedicated Plane for VCCo

Including an optional VCCo plane (continuous, dedicated, or semi-dedicated)
greatly simplifies board layout. It increases the accessibility of routing
connections to power pins and bypass capacitors and provides a low-impedance
path for return currents.

Every Signal Trace is Within One Signal Layer of a Continuous Reference
Plane

Every trace in the stackup should either be adjacent to a reference (power or
ground) plane, or only separated from the closest reference plane by one signal
layer. This ensures that return currents always travel as near as possible to
their corresponding trace. Adjacent signal layers should run in perpendicular
directions so that vertical and horizontal layers alternate.

This limits crosstalk between signal traces of adjacent layers. To maintain
constant impedance from layer to layer, adjust the trace widths for each layer .
See page 3 of XAPP231
for information on calculating the characteristic impedance of a PCB trace based
on its dimensions, or use a field solver. It is important to maintain continuity
of the reference plane. Signal traces should never cross discontinuities (large
hole, slot, or break) in their associated reference plane.

Bypassing

High-frequency Capacitor Within 1 to 2 cm of Each VCC pin

High-frequency bypass capacitors are the smallest capacitors in the bypassing
network. There should be at least one high-frequency capacitor on every VCC/GND
pair, mounted within 1 to 2 centimeters of the VCC pin it is bypassing. The best
location for these capacitors is underneath the PCB, directly beneath the
FPGA.

Capacitor vias should never be shared. Each capacitor requires at least 2
vias connections: one ground, and one Vcc. Vias should descend directly to the
power and ground planes (Do not use traces to connect bypass capacitors to the
power pins they service).

The total capacitance of all high-frequency capacitors must be at least 25
times the equivalent switched capacitance ( C=P/(FV2) for VCCint, C=CLOAD*N for
VCCio). For greater noise immunity, a factor of 50 or 100 should be used instead
of 25. When one capacitor per VCC/GND pin is used, this calculation usually
results in a range of 0.1µF to 0.01µF. Smaller values of 0.0047µF and 0.0033 µF
should also be used.

All high-frequency capacitors should be low ESR ceramic chips. Always use the
smallest package for a given capacitor value. See page 2 of XAPP623
for more information on choosing capacitor size and characteristics. See
capacitor vendors' websites for specific information on capacitor
characteristics (http://www.avxcorp.com/, http://www.tdk.com/).

Mid-frequency Capacitors Within 8cm of VCC Pins

Mid-frequency bypass capacitors are low ESR, low inductance capacitors
ranging from 4.7µF to 47µF. Tantalum capacitors are ideal; aluminum electrolytic
capacitors may also be used. Use at least one for every 3000 slices (two for
V400? four for V1000, 7 for V2000E).

Low-frequency Capacitors Anywhere on PCB

Low-frequency bypass capacitors for board bypassing range from 47 µF to 4700
µF. For this function, any type of capacitor may be used anywhere on the board.

Bypass Capacitor on Each Vref Pin

Because of their high input impedance, Vref pins are succeptible to noise
coupled in from surrounding signals. Every Vref pin needs a local bypass
capacitor ranging from 0.01µF to 0.1µF. Noise from the power supply is not a
concern, so do not use inductors or ferrite beads here.

Simultaneous Switching
Outputs

SSO Guidelines have been Checked

See the datasheet for SSO guidelines. Multiply the number of effective
VCC/GND pairs in your device (value in a chart, by device/package combination),
by the SSO guideline number (value in a chart, by IO standard), to find out the
total number of outputs that may safely be driven. Compute this on a bank by
bank basis. Exceeding these guidelines can lead to serious ground bounce
problems.

Signal Paths (PCB traces and
terminations)

Each Trace has Constant Impedance

Every signal trace should maintain the same impedance no matter where it
goes. Signal traces may be of any practical impedance value (40 ohms to 100 ohms
is common). The same design may have signal traces with a variety of different
impedance values. However, a single trace should not change impedance values
over its length. For example, if a trace starts on one board layer and switches
to another layer, the designer must ensure that the trace on the second layer
has the same impedance as the first. If the layers are different distances from
their respective reference planes, the widths of the signal traces should be
adjusted accordingly. In general, if the distance to the reference plane is
increased, the trace width must also be increased in order to maintain the same
impedance.

Traces Longer Than Tr/6 have been Simulated

The ratio of signal rise/fall time to trace length can determine whether or
not transmission-line effects will occur. In general, long traces with fast
rise/fall times exhibit transmission-line effects. If the time it takes a signal
to propagate down the length of the trace is more than 1/6 of the signal
rise/fall time, transmission-line effects are likely, and the signal path must
be simulated. This can be perfomed in an IBIS or SPICE simulator. For more
information on transmission-line effects and simulation, see the text references
at the end of this document.

If Ringing or Overshoot is Observed, Add Termination
or Change IO Standard

A simulated transmission line that exhibits ringing or overshoot indicates an
unacceptable amount of signal reflection. Signal reflection occurrs when a
signal wave encounters an impedance discontinuity. To repair the ringing or
overshoot, you must eliminate the impedance discontinuity in one of three ways:

Add resistive termination to the PCB (in series or parallel).

Change the SelectIO standard to one with a lower current drive.

Use XCITE DCI (in Virtex-II).

For further information on termination, see our
resources page.

Extra Attention has been Paid to Clock Signals
(GCLK, CCLK, TCK etc)

Clock signals require special attention for two reasons. First, it is
critical that their timing not be marginalized by noise - this can lead to false
clocking of data. Second, clock signals often run at a higher frequency than
data; they can be more troublesome as noise sources. Clock traces and their
drivers should ALWAYS be carefully simulated prior to PCB fabrication.

Long, Closely-spaced Parallel Traces have been Analyzed
for Crosstalk

Pay attention to any traces running in parallel for long distances. Simulate
any suspicious traces using a PCB crosstalk simulation tool to determine if they
will cause problems. If you confirm crosstalk as a problem, manage it by
separating the traces or decreasing their distance from the associated reference
plane (decrease dielectric thickness).

Power Supply and Power
Management

Total FPGA Power Estimated with Power Estimator or
XPower

The Power
Estimator or XPower should be used to determine the approximate power the
FPGA will require. The Power Estimator requires design data generated by MAP
(CLB utilization, Flops, IO standard, BlockRAM usage). XPower is part of the
design flow. These tools provide a guideline for power supply requirements and
are essential for thermal planning.

Power Supply Satisfies POR Monotonicity and Ramp
Rate Requirements

The power supplies should rise from less than 0.1 Vdc to the minimum DC
operating condition voltage level in less than 50 milliseconds, and not faster
than 1 millisecond. The rise should not be inhibited by a current trip, or
current foldback. Current limit behavior is acceptable based on the "Power-On
Ramp Up Current Requirement" specification from the data sheet. The voltage rise
vs. time should be roughly monotonic. Avoid dwelling at a voltage, or having a
'plateau', even if it is acceptable power supply behavior. If the voltage
increases beyond the minimum operating voltage and then drops below it, you will
experience incorrect power behavior. If the power supply voltage falls below the
absolute minimum operating voltage when the device is off, it should not rise
immediately back to the nominal operating voltage when turned on without first
discharging to below 0.1 Vdc. You may need a resistor to bleed off the filter
and bypass capacitor charges to meet this condition.

Power Supply Satisfies POR Minimum Current
Requirement

Aside from meeting the dynamic power requirements determined by the Power
Estimator, the power supply must also be able to supply the minimum
specified startup current specified in the datasheet.

Die Temperature Predicted by TJ = TA + P*QJA is Less
than Max Allowable

Determine the die temperature using the power figure derived from the Power
Estimator, information about the device package, and the maximum ambient
temperature in the operating environment. If it is higher than the maximum
allowable temperature for the device temperature grade (C = Commercial: 0°C -
80°C, I = Industrial: -40°C - 100°C), the design must change (lower ambient
temperature, add heatsink, change package, reduce clock frequency or reduce
device utilization). Further information on thermal planning and management is
located with Advanced
Packaging and on page 1 of XAPP623.

Design for Debug

JTAG header included on board (connected to JTAG pins of
device)

Every PCB should have easy access to FPGA JTAG pins. This enables debugging
in the final system. For best results, route the TCK, TMS, TDI and TDO signals
to a four-pin header on the PCB. This is critical with BG and FG packages which
have limited access to device pins. You may also provide ground and VCC pins in
the header for convenience (six pins).

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