DSP Audio Equalizer
EE697 Final Report
Matt Campbell
Erin Dickman
Jon Vilagy
Advisor: Dr. Vincent Amuso
Senior Design Professor: Paul Jacobs
Sponsors:
Vilagy Incorporated
ENI
Analog Devices
TABLE OF
CONTENTS:
Introduction/Overview ...Page 3
Digital Signal Processor Selection/Overview ....Page 5
DSP Algorithms .Page 8
Power Supply Design Overview Page 10
User Interface Design Overview ...Page 12
Audio Power Amplifier Design Overview Page 14
Group tasks .. .Page 15
Proposed Budget Page 16
Initial Project Proposal for EE697 Appendix 1-1
Master System Schematic .Appendix 1-2
Hardware Block Diagram .Appendix 1-3
Software Block Diagram ..Appendix 1-4
Power Supply Block Diagram ..Appendix 1-5
Overview:
With the increasing power and decreasing cost of digital electronics, primarily VLSI, real time DSP is becoming an economical alternative to tasks formerly realized only by using complex analog filter networks. We would like to demonstrate the flexibility and power of real-time digital signal processing through audio signal equalization.
Digital Signal Processing is becoming commonplace in todays technology. DSP has opened new doors for developers of wireless products, television and radio products, and has benefited the automotive industry as well. The power and flexibility of DSP allows designers to realize tasks that were normally not achievable only one decade ago.
Our intent is to create a DSP audio equalizer, implementing a 10-Band fixed frequency equalizer, as well as incorporating time-alignment functions through delay buffers on the DSP. The system will be controlled by either front panel controls or a wireless infrared remote, with user feedback provided by a matrix LCD panel. Figure 1-1, below, is a hardware block diagram of our proposed design.
Figure 1-1. DSP Equalizer Hardware Block
Diagram
This report describes our design approach for the DSP equalizer, and focuses on all of the major subsystems. The equalizer design is broken down into four categories: DSP Software and Algorithms, Audio Power amplifier, Switch Mode Power supply, and User Interface.
The DSP software section discusses the design and testing of our intended algorithms for the audio equalizer. Included in this section are discussions of our MATLAB simulations and our real-time testing of the DSP.
The Switch Mode Power supply design covers the background of switching power supplies, as well as benefits/tradeoffs to other designs. The power supply design includes a brief discussion of the topology of a switching mode power supply, as well as our proposed specifications.
The Audio Power Amplifier section includes information on the schematic design, as well as tradeoffs and other possible design approaches that were considered in the preliminary stages of Senior Design I.
The user interface portion of this report describes the interface between the LCD and input controls to the DSP, as well as how we intend to allow user inputs into the system.
DSP Hardware
Selection:
The original
proposal for the DSP audio equalizer stated that the equalizer design would be
based on a Texas Instruments TMS320C6211 digital signal processor. The Texas Instruments DSP was offered
from TI bundled in the form of a DSP Starter Kit (DSK). Figure 1-2, below, shows the layout of
our original TI DSK.
Figure 1-2. The Texas Instruments C6211
DSK.
The TI DSK
specifications are as follows:
· 4MB onboard SDRAM data memory
· 128KB Flash Program storage
· TMS320C6211 150MHz Fixed-Point DSP
· 16-Bit, 11 kHz Audio Codec
· Code Composer Studio Software Tools
The choice to use the above-described DSK was based on several factors. After discussing our project with experienced DSP users, we were told that data memory was one of the largest bottlenecks in performing DSP tasks, and that optimizing for maximum use of memory would be difficult. With this in mind, the above DSK proved a good candidate for its abundance (4MB) of SDRAM for Data Storage.
With the core speed of the C6211 DSP at 150MHz, the TI DSP was able to reach a maximum of 1200 MIPS (Million Instructions Per Second). Although this was a fixed point DSP and algorithms to extend the dynamic range of this DSP would slow down the entire DSP program, this would not be enough to affect the relatively low demands of audio filtering.
It was understood when this board was ordered that the onboard audio codec would be insufficient for our design. For CD quality audio, the sampling rate of our audio codec would have to be greater than the nyquist rate for full spectrum audio processing. In this case, the bandwidth of high-fidelity audio is 20kHz, and therefore our sampling rate must be greater than or equal to 40kHz. After some research, a daughter card was found with a suitable audio codec that would interface directly to our DSK.
The daughter card chosen for this task was designed exclusively to interface with all Texas Instruments DSP evaluation modules and starter kits that supported their 80-pin common expansion connector interface. The card was populated with a TLV320AIC27 audio codec, capable of sampling data at rates up to 48kHz, with 18-Bit resolution. The AIC27 codec was capable of supporting CD-quality audio with 96 dB of dynamic range.
Data sheets and specifications for the TI Audio Codec EVM stated that the daughtercard had a glue less interface to TI DSKs, as well as downloadable drivers to interface to the C6211 DSP. After further investigation, it was found that the EVM and DSP interface were not supported by TI, and in fact was not recommended or designed for such a task. Technical support from TI was minimal, and after extensive man-hours into this problem, the decision was made to search for an alternative DSP solution.
After speaking with Professor Jacobs, we began investigating an Analog Devices solution for the DSP. After some research, the Analog Devices ADDU-2106x-EZKIT was chosen as our DSP EVM platform. This EVM was populated with the Analog Devices SHARC ADDU-21061 40MHz floating point DSP. In addition, this board had an onboard audio codec that would meet the requirements of our design. After several phone calls to Analog Devices, the EVM was donated to us by Analog Devices, thus our switch to a new DSP platform would not increase our costs to the project.
The advantages of having such a DSP EVM are two-fold. First, the onboard interface with a CD-quality audio codec simplified the debug required in the equalizer design. With the Texas Instruments board, neither the software nor the hardware was known to be functional, thus making the debug extremely difficult. In this case, the hardware interface is known to be intact, and therefore any debug can be focused onto the software portion of the design. The floating-point topology of the SHARC DSP allows the programmer to generate programs much more efficiently than that of a fixed-point design. The auto-scaling characteristic of a floating point DSP preserves the dynamic range of the system, meanwhile preserving the signal to noise ratio of the system overall at a higher level than the fixed point solution.
The fixed point DSP has special ways of dealing with floating point numbers. In most cases, decimal points are rounded or trigger overflow flags within the DSP. In the case of a real time audio signal, when small signals are present within the system, this rounding of samples after undergoing digital filtering will alter the music severely. This causes the signal-to-noise ratio of the system to increase. In order to avoid this, special programming precautions must be taken to avoid rounding errors, such as multiplying all incoming signals by some factor that eliminates decimal points during matrix convolution.
The Analog Devices SHARC DSP has the following features:
· 40Mhz, Floating Point Core
· Dual High Speed Serial Ports
· Super Harvard Architecture (SHARC). The SHARC architecture allows an instruction and data fetch simultaneously, thus maximizing the use of the 40MHz clock.
· DMA controller for high speed memory access
During performance evaluation of the SHARC DSP, a 256-order butterworth bandpass filter was implemented and tested with a real-time audio signal. The results were astonishing, with the DSP being unaffected by the large number of calculations which it was required to perform.
MATLAB FDAtool (Filter Design and Analysis) was used to design several bandpass filters for this design. The matrices returned from the MATLAB digital filter design were in the form of long (15 decimal) floating point elements. Because the SHARC is a floating point DSP, importing these filters into the DSP software was straightforward.
The Analog Devices EVM was equipped with an onboard high speed RS232 port capable of data rates up to 115,200 bps. This port will be used to communicate with a user interface that is discussed in this report.
DSP Equalizer Algorithms:
The block diagram
shown in figure 1-3, below, shows the block diagram of the equalizer
filtering. The diagram below shows
only five out of ten bands for presentation clarity. The equalizer will contain ten
fixed-frequency digital bandpass filters whose outputs will be scaled and summed
back together to perform the equalization.
The design described below will allow the equalizer to be adjusted
real-time while avoiding coefficient recalculations each time a frequency weight
is adjusted. This will be
beneficial, as we will be adjusting the gain of each filter stage with a PIC
micro controller.
Figure 1-3.
Digital Filter Algorithm of DSP Equalizer
In our proposed design, the gain terms of each of the ten filter bands will be altered real time using a PIC. The PIC will receive its coefficient settings through the user interface. The coefficients are transferred from the PIC to the DSK EVM via RS232 data transfer.
Implementation of the Time alignment functions has not yet been performed, however, our approach to this feature can be viewed in the overall software flow diagram on the next page (Figure 1-4). The operation of the time alignment unit is similar to that of the filter algorithms, where the PIC will load coefficients onto the DSP to tell it quantitatively how much delay it must add to each channel of audio.
Figure 1-4. Master Software Flow Diagram
The reverb and effects unit will allow us to compensate for unevenly placed speakers in a particular room, as well as add 3-D spatialization effects to the audio input stream by delaying only one channel of the stereo audio signal.
We intend to implement our equalizer using 10th order IIR Butterworth bandpass filters. The above designs were implemented in MATLAB with 4th order filters due to limited processing capabilities of our CPU. The filters were tested using a 30-second .wav clip to test for phase distortion/fading problems encountered from summing our filters outputs together. There was no audible distortion detected when using this algorithm, although the hardware will be investigated further using an oscilloscope and spectrum analyzer for us to improve our analysis and investigate any unforeseen problems.
Power Supply:
The power supply design that we
chose to go with was a Switch Mode Power Supply (SMPS). The primary function of
a SMPS is to drive a step down transformer at a much higher frequency than that
of the AC line, using PWM to regulate the transformers outputs. The reason that
a SMPS design was chosen over the linear based design is because the switch mode
designs are smaller, lighter and overall more efficient. When operating at higher frequencies the
smaller the transformer core material needs to be and also less windings are
needed on the transformer itself.
The SMPS is more efficient than the Linear based design because when you
have a linear design the majority of power loss is due to heat dissipation. With
the switch mode design the transistors are basically only operating in the
cutoff and saturation regions, not spending a considerable amount of time in the
linear region and therefore this design is much more efficient. The transformer
will be operating in Flyback mode at a frequency of 200Khz to avoid any audible
harmonics. The transformer in this supply design will be supplying a 9V line at
5A to drive the DSK, LCD and other external components, and also ±40V
lines at 2A to drive the audio power amplifier. The complete schematic of the
SMPS can be seen in the master schematic (Appendix 1-2).
The controller
that was chosen for this is design is the MC34023 from
Motorola/On-semiconductor. The MC34023 is a high speed, fixed frequency,
single-ended pulse width modulated controller optimized for high frequency
operation. This controller is specially designed for Off-line converter
applications which offers us a cost effective solution with minimal components.
They also feature an oscillator, a temperature compensated reference, a wide
bandwidth error amplifier, a high-speed current sensing comparator, and a high
current totem pole output ideally suited for driving a Power MOSFET. The MOSFET
that has been chosen is the MTW7N80E from ON semiconductor. This is a high
voltage n-channel MOSFET that uses an advanced termination scheme to provide
enhanced voltage-blocking capacity without degrading the performance over
time. It is designed for high speed
switching applications in power supplies and offer additional safety margin
against unexpected voltage transients. Because this MOSFET is so robust there is
not a need for an additional snubber circuit preceding the transformer. This FET can easily handle any back EMF
that may be generated from the transformer.
The controller
will regulate the supply with respect to the +40V Amplifier supply line though
an opto-isolator. It was decided to regulate with respect to the amplifier
supply line because this is where we can see the large change in current and
voltage. The Amp by far will be using the most power. An opto-isolator was
chosen because if there was a large current was drawn out of the supply by the
amplifier, there would be a large voltage drop across the secondary of the
transformer that the controller would then have to compensate for this drop. We
are also regulating with the opto-isolator to protect the DSK from a voltage
drop in the rectifier after the transformer. If the voltage from the rectifier
dropped too low than there would be a possibility of getting current flow out of
the controller that would burn the DSK.
The overall block diagram of the Switch Mode Power Supply can be seen in Figure 1-5, below.
Figure 1-5. Power Supply
Block Diagram
Equalizer User
Interface:
The equalizer user interface consists of a PIC16F877 micro controller, front panel switches, and a 4 Line by 20 Character Matrix LCD display. The PIC will be used to control the LCD Display, along with reading commands from the input switches, and interfacing to a second PIC that will be programmed to decode a wireless infrared remote control.
The 877 microcontroller contains 8K of Flash programmable memory. This particular controller was chosen not because of its extensive I/O available, but for the amount of data storage that we would require holding all of the user menus on the PIC. The PIC will hold the complete user interface software for the system, and will simply load the respective equalizer coefficients into the DSK via an RS232 serial link, thus relieving the DSP of updating the matrix display or reading the front panel switches.
Figure 1-4, below, shows a picture of the matrix LCD in operation as driven by the PIC. Several menu screens will be developed to select the weights of each frequency in the DSP equalizer, as well as the time delay settings. The wireless infrared remote will be used to control several of these functions as well, although it may be reconfigured so that each button on the remote will perform a specific task, rather than scroll through menus on the display. The purpose of configuring the system in this particular way is so that our user does not have to be within close proximity of the equalizer while adjusting its settings.
Figure 1-4. User Interface LCD Display driven by the
PIC16f877
The LCD display that we intend to use on this project utilizes the Hitachi HD44780 controller chipset. Time permitting, we intend to program the CGRAM (Character Generator Random Access Memory) to hold solid bar characters that will allow us to use the display as an audio spectrum analyzer when the equalizer settings are not being adjusted.
The wireless
remote control was originally intended to be implemented using an IR
receiver/transmitter chipset by Holtek Semiconductor. The chipset featured a 4-Bit data
transmit/receive system, as well as an 8-Bit encryption word to avoid
interference from other remote controls using the same modulation frequency
(40kHz), for a total of 12 bits being transmitted in one data packet. Although this design approach has not
been completely phased out, we have decided after discussion with Professor
Jacobs that the same functions could be implemented using a PIC to decode a
standard IR remote control that would normally be used for a TV or stereo. The PIC16F84A was chosen to perform this
task, and the IR transmitter we intend to use is a universal remote control
manufactured by Philips Magnavox.
After discussing the IR remote control system with another similar design
team, we were told that Philips universal remotes provide the cleanest signal
output of all brands. This
was briefly verified in the lab using several remotes from different
manufacturers, a 40kHz IR receiver, and an oscilloscope.
Our intention of using an isolated PIC for the IR receiver program was based on the fact that multitasking within a PIC controller is not a trivial task. Time permitting, the code written for the IR receiver will be ported over to the master PIC (16F877) to minimize the amount of hardware on the user interface circuit. Multi-threading of the LCD drivers, the RS232 communications, and IR decoder software at this point would be an enormous task.
Because we are using a modular approach for our user interface (Separate controllers for IR and LCD), the PIC IR decoder can easily be replaced by the Holtek HT-12D decoder chip if we are unsuccessful at keeping high noise immunity in our infrared signal decoder algorithms.
To interface the 877 microcontroller to the DSP evaluation board, a MAX232 RS232 line driver will be implemented. The MAX232 has an on-board charge pump voltage converter to allow TTL level signals from the PIC to drive an RS232 Line. The DSP EVM has a serial line driver on board as well, and therefore calls out the need for the MAX232 on our end of the interface.
Stereo Audio Power
Amplifier:
At the beginning of December, we became interested in incorporating a stereo power amplifier with our equalizer so that external components would not strictly be necessary for operation. There were two main choices for design methodology, a design consisting solely of discrete components (the approach the audio power amplifier team is pursuing) or an IC design using packages available from several distributors. These two options were researched concurrently for the period of one month.
During the initial research period, several ICs were discarded as being unsuitable due to high distortion or inefficiency (such as Sanyos STK-084 and Philips TDA packages). Discrete research showed that a completely self-designed power amplifier would take a large amount of research and troubleshooting, with many considerations to take into account such as the choice of BJTs vs. FETs (larger gain vs. self-biasing and higher noise resistance), proper biasing to reduce distortion, and placement and design to minimize frequency and phase distortion, among other things such as heat dissipation and thermal protection. At this point an IC design began to become more desirable since the amplifier is not a major portion of our project and we wished to dedicate our time to development of the DSP software.
Several ICs manufactured by National Semiconductor seemed appropriate for our use. The LM3886 was selected for its moderate power output (38W RMS into an 8 Ohm load) and low distortion (0.03% at 30 W, 0.1% at full load), and samples were ordered at no cost through the National website. An initial concern was whether or not a switching power supply would work well with a power amplifier due to its high power consumption, but research showed that switch mode power supplies do work and are in fact the dominant design used in modern amplifiers.
Professor Jacobs
and Dr. Amuso approved the IC approach on the fifteenth of January, and the
discrete design was discarded.
External parts for the IC were purchased locally and a mono prototype was
constructed on the sixteenth.
Refer to the master schematic (Appendix 1-2) for the complete amplifier
design. The mute switch was shorted for testing, and the L/R combination seen at
the output is to account for highly capacitive loads that could be present with
very long speaker leads. The
prototype is fully operational; however, at low supply voltages or at full
volume with the maximum supply, the amp shuts down and it is necessary to cycle
power to reset it. This problem is
still being researched, but is most likely due to the activation of one of the
ICs internal protection schemes.
We are pleased in general with the volume level and absence of noise
currently present. The second
prototype will consist of two identical circuits for stereo operation on a
copper board, and parts have already been obtained from All Electronics
Corporation.
DSP Equalizer Team -
Member Tasks:
Matt
Campbell
DSP algorithms +
implementation
Audio Power
Amplifier design
Wireless
Remote
Jon
Vilagy
DSP
algorithms + implementation
DSP low
level drivers
User
interface: Front Panel Controls, LCD interface to the DSP using a PIC for
control
Erin
Dickman
Switching-Mode
Power Supply Design
Group
Webmaster
OrCAD PCB
Layouts
for final prototype
DSP Audio
Equalizer Proposed Budget:
TI C6211 DSP
Module
$200
TI Audio Codec
EVM
$100
Analog Devices
SHARC EVM
$175
LCD, Wireless
IR Remote
$150
Power
Supply
$150
Audio Power
Amp
$100
Chassis
$90
Anticipated Total Cost:
$965
The above costs have been defrayed
by our sponsors: Analog Devices, ENI, and Vilagy
Incorporated.
Special thanks to our sponsors on this project, without your support, our project could not be completed.