Host port
The host port is used to manage and monitor the CobraNet interface. Electrical operation and protocol is detailed in the Host Management Interface documentation. These are un-buffered 56K host port signals.
| Description |
Module Signal |
Reference Design Signal |
Direction |
Notes |
| Host Data |
Data[7-0] |
Data[7-0] |
In/Out |
Host port data |
| Host Address |
Addr[2-0] |
Addr[2-0] |
In |
Host port address |
| Host Direction |
R/W# |
R/W# |
In |
Host port transfer direction |
| Host Request |
HREQ# |
HREQ# |
In |
Host port DMA request |
| Host Alert |
HACK# |
HACK# |
Out |
Host port interrupt request |
| Host Select |
HDS# |
HEN# |
In |
Host port "chip" select |
SCI port
Asynchronous serial data streams may be transparently bridged across the network using the SCI port. 8 and 9 bit formats are supported at baud rates up to 57.6K. Multi-drop network mode (RS-485) is also supported (SCLK serves as transmitter enable). These are un-buffered 56K SCI (Serial Communications Interface) signals.
| Description |
Signal |
Direction |
Notes |
| Asynchronous receive |
RXD |
In |
|
| Asynchronous transmit |
TXD |
Out |
|
| Asynchronous transmit enable |
SCLK |
In/Out |
|
Synchronous Serial (Audio)
The synchronous serial interfaces are used to bring digital audio into and out of the system. Typically the SSI is wired to ADCs and/or DACs. Detailed SSI timing and format is described in Synchronous Serial Interface Data Format.
| Description |
Signal |
Direction |
Notes |
| Audio bit clock |
SCK |
In/Out |
Synchronous serial bit clock. Depending on audio interface mode of operation, this is 256FS (8x4 channels), 128FS (4x4 channels) or 64FS (2x4 channels). |
| Audio output data |
DOUT[3-0] |
Out |
Output synchronous serial audio data |
| Audio input data |
DIN[3-0] |
In |
Input synchronous serial audio data |
Audio Clocks
See Synchronization Modes for an overview of synchronization modes and issues. See Synchronization Control Variables for details on the applications of these synchronization signals.
| Description |
Module Signal |
Reference Design Signal |
Direction |
Notes |
| Sample clock |
FS1 |
EXTWRDCLKOUT |
Out |
Sample clock (1FS) is present at this output while the interface is connected to the network and operating properly. |
| Sample clock cascade |
REFCLK |
EXTFS |
In |
Allows synchronization of FS[256..1] divider chain to external source. |
| Reference clock |
REFCLK |
EXTWDRCLKIN |
In |
Auxiliary reference clock input for synchronizing network to an external clock source and for redundancy control. |
| Master audio clock input |
FS512IN |
EXTFS256 |
In |
External master clock input for systems containing multiple CobraNet™ interfaces |
| Master audio clock output |
FS512OUT |
FS256 |
Out |
Master clock output. Note that Module uses a faster master clock than reference design |
| Derived audio clocks |
n.a. |
FS[128..1] |
Out |
All binary divisors of master audio clock |
Indicators
| Module Indicator |
Reference Design Indicator |
Description |
| flashing green indicator |
TRANSMIT_LED |
Transmission onto Ethernet in progress (hardware [PHY] controlled signal) |
| flashing green indicator |
RECEIVE_LED |
Activity on Ethernet detected (hardware [PHY] controlled signal) |
| solid or flashing green indicator |
LINK_LED |
Valid connection to Ethernet (hardware [PHY] controlled signal) |
| n.a. |
100/10_LED |
100Mbit Ethernet connection (hardware [PHY] controlled signal) |
| n.a. |
RX_ERROR |
Receive error condition (firmware controlled signal). |
| n.a. |
TX_ERROR |
Transmit error condition (firmware controlled signal). |
| yellow indicator |
CONDUCTOR |
Indicates interface is providing master clock for the network (firmware controlled signal). |
| red indicator |
FAULT |
Indicates internal fault detected in interface (firmware controlled signal). |
Miscellaneous
| Description |
Module Signal |
Reference Design Signal |
Direction |
Notes |
| Reset |
Reset# |
!RESET |
In |
System reset (active low) |
| Watch dog |
WatchDog |
!WATCHDAWG |
Out |
Pulses at 750Hz nominal rate to indicate proper operation. A duration in excess of 200ms indicates hardware or software failure has occurred and the interface should be put into reset. |
| Interface ready |
Mute# |
n.a. |
Out |
Asserts (active low) during initialization and when fault detected or connection to network is lost |
| Cable power |
AuxRJ4 - 8 |
n.a. |
In/Out |
Aux RJ-45 pins |
| Debugger reset |
n.a. |
!ONCE_RST |
|
Indicates a reset request has been received from the OnCE debugging interface. This should be wired back to !RESET in some way. Module contains integral circuitry for supporting debug reset. |
Power
| Module Power |
Reference Design Power |
Description |
Specification |
| VCC_+3 |
n.a. |
System digital +3.3v |
3.3 +/-0.25v, 1.2A |
| VCC_+5 |
n.a. |
System digital +5.0v |
5.0 +/-0.25v, 0.1A |
| n.a. |
VCC |
System digital +5.0v |
5.0 +/-0.25v, 2.0A |
| GND |
GND |
System ground |
|
